DAQ for CMS RPC chambers test

	T.Anguelov, I.Atanasov, V.Genchev, G.Georgiev, G.Sultanov
	INRNE - BAS, Sofia
	L.Litov, B.Pavlov, I.Peev, P.Petkov
	Sofia University, Sofia

Talk given at the JINR XVIII International Symposium on Nuclear Electronics & Computing (NEC'2001) September 12-18, 2001, Varna, Bulgaria

Abstract

Part of the Resistive Plate Chambers (RPC)[1] for the barrel muon system of the CMS detector at LHC accelerator at CERN will be produced by CMS Sofia collaboration and tested in cosmic muons in order to study their performance at different running conditions. The data acquisition system (DAQ) developed to handle the signals generated by the RPC is described. 

_______________

This work is supported by the Bulgarian Ministry of Education and Science

	
	Introduction
	
The Compact Muon Solenoid (CMS)[2] Collaboration has chosen the Resistive Plate Chambers as dedicated detectors for the first level muon trigger system. The RPC are gaseous parallel-plate chambers that combine a reasonable level of spatial resolution with excellent time resolution, comparable to that of scintillators.    An RPC consists of two parallel plates, made out of phenolic resin (bakelite) with a high bulk resistivity , separated by a gas gap of 2 millimeters. The whole structure is made gas tight. The outer surfaces of the resistive material are coated with conductive  graphite paint to form the HV and ground electrodes. The read-out is performed by means of aluminum strips separated from the graphite coating by an insulating PET film. The RPC proposed for CMS is made of two gaps with common pick-up strips in the middle, the so called double gap RPC. In this case the total induced signal read out by the Front End electronics is the sum of the two single-gap signals. The chambers will be  operated in the so called avalanche mode  with    96% C2H2F4 based mixture and 4% i-C4H10. The RPC produced by CMS Sofia collaboration are 250 x 150 cm**2 in area and have 2 x 96 read-out channels per chamber.
The RPC has to fulfill three basic requirements: good time resolution, high efficiency and uniformity and low cluster multiplicity. To test the performance of the RPC, a dedicated experimental set-up will developed. Five chambers will be placed between two trigger scintillator layers able to determine the impact point on the RPC of the incoming cosmic muons, so the total number of readout channels will be 960. The efficiency will be defined as the ratio between counting rate of the signals and trigger rate.
In this report we describe the specific readout system designed to process the RPC signals.

	Front end 

Each RPC embodies front end (FE) electronic modules, which accepts signals from chamber electrodes (strips). The FE accepts the signals from up to 16 strips. After amplification, pulse formatting and level translation the FE outputs to the upper level individual information for each strip as LVDS 100nS pulse. This pulse originate either a muon crossing or noise due to HV discharge. For test purposes the FE accept a 4 bit test pattern. Each bit of that pattern activates four LVDS outputs simultaneously.

	The readout system
	
Each chamber is equipped with 12 Front-End (FE) boards tied to one CANAC module. A FE board handles signals from up to 16 strips. A single channel consists of two-stage amplifier, threshold discriminator, one-shot and line-driver. At the output a LVDS signal is generated over twisted pair copper. The signal has a voltage of  250 mV on 110 Ohms. They are read out by CAMAC modules. The block diagram of the readout system is given on fig. 1. 
The CAMAC modules (fig. 2) are designed to accep signals from FE boards. Each CAMAC module embodies two FPGA devices (Virtex-E from Xilinx) and can receive signals from one RPC chamber. The CAMAC modules are controlled by a microcontroller – 

PIC16F877 by Microchip. The PIC is responsible for initialization, mode set up, read out of CAMAC modules and communication with a PC via serial interface. It reads the Virtex devices via serial bus, presenting to to a personal computer (PC)  information for the flashed strips for each RPC chamber. The PIC uses PC serial port at 115000 Kbps. This spead is sufficient for acquisition of data from five RPC chambers with cosmic muons (~ 70  muons/m**2*sec). The incoming data will be processed by the PC using  LabVIEW from NATIONAL INSTRUMENTS.
The Virtex devices can act in two operational modes – data aquisition or noise mesurement. They also provide a test pattern to FE for test porpoises.  
In acquisition mode the DAQ requires external signal (trigger) for timing synchronization. This signal is generated by trigger electronics. Each trigger generates an interrupt to PIC, thus the PIC can start read out of all Virtex devices. Upon receiving a trigger the Virtex devices latch data from FE and store them in a shift register for read command from PIC. The PIC read all Virtex devices via dedicated serial interface. Every strip of  RPC chambers is unitary encoded into outgoing serial word from the Virtex device. When the strip is “hit”, its corresponding bit is set, so the PIC can scan all Virtex devices to obtains information for all strips, affected by current muon crossing.
In noise measurement mode the Virtex devices  require a no trigger. In this mode signals from RPS increment corresponding internal counters for a specified period of time. In order to minimize the number of counters, signals from eight consecutive strips are OR-ed and tied to one 16 bit counter. The counters have a “overflow” indicator as MSB.
Some of RPC use less than 16 of the available inputs of the standard FE. In order to mask unused FE channels any Virtex can accept a variable number of channels from one FE. Masking undesirable channels can be used to test only part of RPC.
Every Virtex device has unique jumper selectable 4 bit address. The PIC read out either a part of  Virtex devices or all of them. The higher address is reserved for subset of command, which have to be executed simultaneously by all devices – broadcast.
The PIC module drives the Xilinx devices through a simple synchronous serial bus with separated receive and transmit wires. Synchronization clock is delivered from microprocessor clock divided by 4. The PIC module acts as a master on the bus, starting a bus operation activating a Xon/Xoff signal. The bus command begins by a leading byte which contains four bit address and for bits command code. If the command code specifies a data transfer the leading byte is followed by data with corresponding length and direction. Currently implemented commands to the Virtex devices are listed in Table 1.

										Table 1.

Command	Direction	Data	Broadcast	
Load mask	To Virtex	6 bytes	Yes	
Load test data	To Virtex	2 bytes	Yes	
Send test data to FE	To Virtex	No	Yes	
Enable noise counters	To Virtex	No	Yes	
Disable noise counters	To Virtex	No	Yes	
Read noise counters	From Virtex	12 bytes	No	
Read RPC data	From Virtex	6 bytes	No	
Start acquisition 	To Virtex	No	Yes	
Reset 	To Virtex	No	Yes	

On request from the PC the PIC module executes one or a sequence of commands listed above to  perform desired task. At start up the PIC can optionally load mask to suspend data from non existing strip and send test data to FE to check data integrity. DAQ, brought in acquisition mode, is waiting for a trigger to latch data from RPC’s and send them to the PC. A user specified period of time is need when DAQ collects noise information.

Conclusions

Due to reprogrammability of FPGA devices used as destination for the signals from front end system, the input level, inernal structure and function can be easy changed or upgraded. The use of  reprogrammable microcontroller gives flexibility in the algorithm of handling input data and versatility in selftest of DAQ itself.

References

1.The Muon Project, Technical Designe Report, CERN/LHCC 97-32, CMS TDR 3, 15 December 1997.
2. The Compact Muon Solenoid (CMS), Technical Proposal, CERN/LHCC 94-38, LHCC/P1, December 1994.
3. Virtex-E Field Programmable Gate Arrays, February 19, 2000 (Version 1.0), XILINX.